1. Field of Invention
The present invention relates generally to the field of integrated circuit synthesis, and more particularly to a method for designing and implementing deep sub-micron integrated circuits.
2. Discussion of Background
The Semiconductor Industry Association's (SIA) 1997 National Technology Roadmap for Semiconductors (NTRS) (www.scmichips.org) looked at the challenges the semiconductor industry would have to overcome in order to sustain the rapid technology development it has enjoyed in the past several years. The NTRS report concluded that the industry is rapidly approaching a formidable “100 nm barrier” that threatens the continuation of the historical success the industry has enjoyed. The most alarming finding of this working group was that the industry has become very “idea limited,” and almost all areas of design technology would hit a brick wall by the year 2006, when the industry anticipates the first shipment of 100 nm technology.
Before any revolutionary solutions are available to combat this crisis, innovations are still required to solve the immediate problems of keeping up with the requirements till the year 2006. The NTRS predicts that overall design productivity has to improve by about 10% every year, overall design cycle times have to improve by 25% every year, 60% of the design content will need to be reusable, and that synthesis and physical design need to be coupled (including asynchronous logic).
The Gigascale Silicon Research Center (GSRC, www.gigascale.org), a center funded by SIA/SEMATECH to conduct potentially long-lead research into this problem, categorized the problems identified in the 1997 NTRS as:                Problems of the Small: issues related to small device geometry and the evolving role of interconnect and communication among devices and subsystems        Problems of the Large: related to the large systems that go on a chip, including design, verification and testing of large systems        Problems of the Diverse: Issues related to the diversity of subsystems on a chip, including digital, analog. RF and memory devices.        
Many tools have been created to address the various issues that need to be solved in order to overcome the nano-metric challenge. These include the Epsilon project (Sophia R&D group), the PKS product (Ambit group), QPOpt/PBOpt family of transformations (DSM group), the Signal Integrity initiatives in SE/Ultra and various other design and verification initiatives.
However, it has become very clear that even if the various components of a design automation toolset could handle specific issues in their respective domain, the overall problems of size, diversity and productivity may not he solved unless a coherent and comprehensive approach to tools working together in a convergent flow is taken.
Also, for “deep sub-micron” (DSM) manufacturing processes (i.e. those less than or equal to 0.18 micron), the problem of wire delay becomes a significant issue. Prior to DSM, most of the delay on a chip was due to the logic gates, and the delay associated with the wires was relatively insignificant. However, for 0.18 micron processes, the delay of the wires is at least equal to the delay in the gates, and at 0.13 micron technology, the wire delay becomes dominant. This is a significant paradigm shift and requires a new design methodology in order to properly address the new issues raised. Further complicating 0.13 micron design, is that there are now 6 metal layers (horizontal and vertical pairs which produce three different wire levels) in which to route the wires. Each layer has a different thickness, resulting in wires of different maximum speeds (fast, medium and slow). Thus, a designer must now also decide which wire layer is appropriate for each wire.
The problem of wire delay dominance can cause serious problems for standard prior art design techniques. Using traditional techniques, integrated circuits (hereinafter “chips”) are generally designed using logic blocks (modules) comprising 10,000–50,000 gates. Modern designs having 10 million or more transistors are simply too large for current design tools to handle, so the designs are broken down in manageable blocks. A design is created using an RTL (register transfer level) design tool such as Verilog or VHDL. This describes the design in terms of functionality at cycle boundaries. The design is then synthesized and the logic optimized for each logic block (local optimization). Finally, the design is physically synthesized, which is the first time that the whole chip is considered. The physical synthesis process comprises actually placing the blocks and routing the wires.
Each stage (RTL, logic synthesis, physical synthesis) generally takes several weeks. After the process is complete, certain wires will be too long (i.e. too much delay), so the whole process must be repeated. However, as a result of the re-design some other wires now have too much delay. This problem is known in the industry as the “timing convergence” problem. According to some empirical studies, it generally takes 50 iterations in order to complete a design. At several weeks per iteration, the design cycle time is a significant factor in the cost and delay in the design and implementation of a chip. When the wire delays actually become dominant for DSM designs, the timing convergence problem is seriously exacerbated.
Thus, it would be desirable to have an improved design methodology to reduce the design cycle time for the design and implementation of deep sub-micron integrated circuits.